Many differential amplifiers have two stages and thus have two poles in their frequency response. The second pole for a two-stage differential amplifier lowers the unity gain frequency and thus degrades the bandwidth and phase margin for the amplifier. But a relatively large phase margin in important to allow the amplifier to respond quickly to any transient disturbances. A stable two-stage differential amplifier design thus forces the second pole frequency as high as possible to increase the unity gain frequency and operating stability. But the increased phase margin then comes at the cost of increased power consumption.
The conflict between providing an increased unity gain frequency and reducing power consumption may be better appreciated through a consideration of a conventional two-stage differential amplifier 100 shown in FIG. 1. A first stage includes a p-type metal oxide semiconductor (PMOS) transistor P1 having a drain connected to the drain of an n-type metal oxide semiconductor (NMOS) transistor M1. Similarly, the first stage includes a PMOS transistor P2 having a drain connected to the drain of an NMOS transistor M2. A differential input signal formed by the difference between a positive input signal inp and a negative input signal inn drives the first stage. In particular, positive input signal inp drives the gates of transistors P2 and M2 whereas negative input signal inn drives the gates of transistors P1 and M1. A PMOS transistor P5 having its gate driven by a first bias signal pbias connects between the sources of transistors P1 and P2 and a power supply rail supplying a power supply voltage VDD. To complete the first stage, an NMOS transistor M5 having its gate driven by a second bias signal nbias connects between the sources of transistors M1 and M2 and ground.
A second stage for two-stage differential amplifier 100 includes a PMOS transistor P3 having a source connected to the power supply rail and a drain connected to a drain of an NMOS transistor M3 having its source tied to ground. The drains of transistors M1 and P1 in the first stage act as an input node for the second stage and are thus tied to the gates of transistors P3 and M3. A capacitor C and a resistor R are connected in series between this input node and the drains of transistors P3 and M3 for compensation. Similarly, the second stage also includes a PMOS transistor P4 in series with an NMOS transistor M4 that respond to the drains of first stage transistors P2 and M2. Another capacitor C in series with a resistor R compensates the response of transistors P4 and M4. The drains of transistors P4 and M4 form a positive output node whereas the drains of transistors P3 and M3 form a negative output node.
The resulting two-stage operation is quite advantageous since each stage includes complementary pairs of PMOS and NMOS transistors and thus has a double transconductance boost in gain as compared to single transistor (Class A amplifier) architectures. In addition, the pole from the second stage has its frequency boosted by the increase in gain for the second stage, which increases the unity gain frequency (increased phase margin) and stability for two-stage differential amplifier 100. But note that the current consumption for the second stage is not controlled by any bias transistors such as transistors P5 and M5. Two-stage differential amplifier 100 will thus have relatively high power consumption that is also subject to process variations.
Another conventional two-stage differential amplifier 200 is shown in FIG. 2. The first stage is as discussed with regard to two-stage differential amplifier 100. But the second stage differs in that the source of transistor P3 couples through a PMOS transistor P6 to the power supply rail. Similarly, the source of transistor P4 couples to the power supply rail through a PMOS transistor P7. A bias signal pbias2 drives the gates of transistors P6 and P7 to control the amount of current used by the second stage. Two-stage differential amplifier 200 thus consumes less power than two-stage differential amplifier 100 and is less subject to process variations. But this increase in power efficiency comes at the cost of the degeneration in transconductance for transistors P3 and P4 by the resistance presented by transistors P6 and P7, respectively. This second pole frequency for two-stage differential amplifier 200 is thus reduced compared to two-stage differential amplifier 100. This reduction in second pole frequency reduces the unity gain frequency and thus reduces the stability and phase margin.
There is thus a need in the art for a two-stage differential amplifier with low power consumption and a relatively high unity gain frequency.